Don't use stats register; refer to uarch counters by number

[riscv-tests.git] / benchmarks / common / syscalls.c

diff --git a/benchmarks/common/syscalls.c b/benchmarks/common/syscalls.c
index c8688ebe279eaf86009c4ff78fc1cf87a7b32b35..87fd358ce0c17c2cb110254a6057cdaf9a8b49ce 100644 (file)
--- a/benchmarks/common/syscalls.c
+++ b/benchmarks/common/syscalls.c
@@ -1,3 +1,5 @@
+// See LICENSE for license details.
+
 #include <stdint.h>
 #include <string.h>
 #include <stdarg.h>
@@ -20,8 +22,8 @@ static long handle_frontend_syscall(long which, long arg0, long arg1, long arg2)
   magic_mem[2] = arg1;
   magic_mem[3] = arg2;
   __sync_synchronize();
-  write_csr(tohost, (long)magic_mem);
-  while (swap_csr(fromhost, 0) == 0);
+  write_csr(mtohost, (long)magic_mem);
+  while (swap_csr(mfromhost, 0) == 0);
   return magic_mem[0];
 }
 
@@ -37,9 +39,6 @@ static long counters[NUM_COUNTERS];
 static char* counter_names[NUM_COUNTERS];
 static int handle_stats(int enable)
 {
-  //use csrs to set stats register
-  if (enable)
-    asm volatile ("csrrs a0, stats, 1" ::: "a0");
   int i = 0;
 #define READ_CTR(name) do { \
     while (i >= NUM_COUNTERS) ; \
@@ -47,33 +46,31 @@ static int handle_stats(int enable)
     if (!enable) { csr -= counters[i]; counter_names[i] = #name; } \
     counters[i++] = csr; \
   } while (0)
-  READ_CTR(cycle);   READ_CTR(instret);
-  READ_CTR(uarch0);  READ_CTR(uarch1);  READ_CTR(uarch2);  READ_CTR(uarch3);
-  READ_CTR(uarch4);  READ_CTR(uarch5);  READ_CTR(uarch6);  READ_CTR(uarch7);
-  READ_CTR(uarch8);  READ_CTR(uarch9);  READ_CTR(uarch10); READ_CTR(uarch11);
-  READ_CTR(uarch12); READ_CTR(uarch13); READ_CTR(uarch14); READ_CTR(uarch15);
+  READ_CTR(mcycle);  READ_CTR(minstret);
+  READ_CTR(0xcc0); READ_CTR(0xcc1); READ_CTR(0xcc2); READ_CTR(0xcc3);
+  READ_CTR(0xcc4); READ_CTR(0xcc5); READ_CTR(0xcc6); READ_CTR(0xcc7);
+  READ_CTR(0xcc8); READ_CTR(0xcc9); READ_CTR(0xcca); READ_CTR(0xccb);
+  READ_CTR(0xccc); READ_CTR(0xccd); READ_CTR(0xcce); READ_CTR(0xccf);
 #undef READ_CTR
-  if (!enable)
-    asm volatile ("csrrc a0, stats, 1" ::: "a0");
   return 0;
 }
 
-static void tohost_exit(int code)
+void tohost_exit(long code)
 {
-  write_csr(tohost, (code << 1) | 1);
+  write_csr(mtohost, (code << 1) | 1);
   while (1);
 }
 
 long handle_trap(long cause, long epc, long regs[32])
 {
   int* csr_insn;
-  asm ("jal %0, 1f; csrr a0, stats; 1:" : "=r"(csr_insn));
+  asm ("jal %0, 1f; csrr a0, 0xcc0; 1:" : "=r"(csr_insn));
   long sys_ret = 0;
 
   if (cause == CAUSE_ILLEGAL_INSTRUCTION &&
       (*(int*)epc & *csr_insn) == *csr_insn)
     ;
-  else if (cause != CAUSE_SYSCALL)
+  else if (cause != CAUSE_MACHINE_ECALL)
     tohost_exit(1337);
   else if (regs[17] == SYS_exit)
     tohost_exit(regs[10]);