Add HW breakpoint test

[riscv-tests.git] / benchmarks / common / util.h

diff --git a/benchmarks/common/util.h b/benchmarks/common/util.h
index 638f02419304705a704fe841c35639fe8e6e0d48..c35bf7cde831b39354e7da5791737694840adb54 100644 (file)
--- a/benchmarks/common/util.h
+++ b/benchmarks/common/util.h
@@ -1,3 +1,5 @@
+// See LICENSE for license details.
+
 #ifndef __UTIL_H
 #define __UTIL_H
 
@@ -31,6 +33,8 @@ static void setStats(int enable) {}
 extern void setStats(int enable);
 #endif
 
+#include <stdint.h>
+
 extern int have_vec;
 
 #define static_assert(cond) switch(0) { case 0: case !!(long)(cond): ; }
@@ -109,6 +113,12 @@ static void __attribute__((noinline)) barrier(int ncores)
   __sync_synchronize();
 }
 
+static uint64_t lfsr(uint64_t x)
+{
+  uint64_t bit = (x ^ (x >> 1)) & 1;
+  return (x >> 1) | (bit << 62);
+}
+
 #ifdef __riscv
 #include "encoding.h"
 #endif
@@ -116,9 +126,9 @@ static void __attribute__((noinline)) barrier(int ncores)
 #define stringify_1(s) #s
 #define stringify(s) stringify_1(s)
 #define stats(code, iter) do { \
-    unsigned long _c = -rdcycle(), _i = -rdinstret(); \
+    unsigned long _c = -read_csr(mcycle), _i = -read_csr(minstret); \
     code; \
-    _c += rdcycle(), _i += rdinstret(); \
+    _c += read_csr(mcycle), _i += read_csr(minstret); \
     if (cid == 0) \
       printf("\n%s: %ld cycles, %ld.%ld cycles/iter, %ld.%ld CPI\n", \
              stringify(code), _c, _c/iter, 10*_c/iter%10, _c/_i, 10*_c/_i%10); \