Fix dhrystone timing code

[riscv-tests.git] / benchmarks / dhrystone / dhrystone.h

diff --git a/benchmarks/dhrystone/dhrystone.h b/benchmarks/dhrystone/dhrystone.h
index 767a65728b796ab462b593071ed2f39060a27bcb..37535e77beec2d81ab826177ec16dcf6dca98447 100644 (file)
--- a/benchmarks/dhrystone/dhrystone.h
+++ b/benchmarks/dhrystone/dhrystone.h
@@ -381,7 +381,7 @@ extern clock_t      clock();
 
 #elif defined(__riscv)
 
 
 #elif defined(__riscv)
 

-#define HZ 976563
+#define HZ 1000000

 #define Too_Small_Time 1
 #define CLOCK_TYPE "rdcycle()"
 #define Start_Timer() Begin_Time = rdcycle()
 #define Too_Small_Time 1
 #define CLOCK_TYPE "rdcycle()"
 #define Start_Timer() Begin_Time = rdcycle()