Merge pull request #21 from sifive/add_freedom_sim_targets

[riscv-tests.git] / debug / README.md

diff --git a/debug/README.md b/debug/README.md
index 09662ba0be57809193b3bc675b8a791ef587fcf5..56f69db07ec6a1cf6c009a97d1d1314b6b860834 100644 (file)
--- a/debug/README.md
+++ b/debug/README.md
@@ -19,10 +19,16 @@ Targets
 
 `./gdbserver.py --spike32 --cmd $RISCV/bin/spike`
 
-32-bit SiFive Core on Microsemi FPGA board
-------------------------------------------
+32-bit SiFive Core on Supported FPGA Boards &  Hardware
+-------------------------------------
+
+`./gdbserver.py --freedom-e300`
+
+32-bit rocket-chip core in Simulation
+-------------------------------------
+
+`./gdbserver.py --freedom-e300-sim`
 
-`./gdbserver.py --m2gl_m2s`
 
 Debug Tips
 ==========
@@ -36,3 +42,6 @@ to get an idea of what might have gone wrong.
 You can see what spike is doing by add `-l` to the spike command, eg.:
 `./gdbserver.py --spike32 --cmd "$RISCV/bin/spike -l"
 DebugTest.test_breakpoint`. (Then look at spike.log.)
+
+You can run gdb under valgrind by passing --gdb, eg.: `./gdbserver.py --spike64
+--gdb "valgrind riscv64-unknown-elf-gdb" -- -v DownloadTest`.