Merge pull request #21 from sifive/add_freedom_sim_targets

[riscv-tests.git] / debug / README.md

diff --git a/debug/README.md b/debug/README.md
index 4a90c0c770aad9157da31f720ef60d689d141639..56f69db07ec6a1cf6c009a97d1d1314b6b860834 100644 (file)
--- a/debug/README.md
+++ b/debug/README.md
@@ -19,11 +19,17 @@ Targets
 
 `./gdbserver.py --spike32 --cmd $RISCV/bin/spike`
 
-32-bit SiFive Core on Arty FPGA board
+32-bit SiFive Core on Supported FPGA Boards &  Hardware
 -------------------------------------
 
 `./gdbserver.py --freedom-e300`
 
+32-bit rocket-chip core in Simulation
+-------------------------------------
+
+`./gdbserver.py --freedom-e300-sim`
+
+
 Debug Tips
 ==========