Merge pull request #21 from sifive/add_freedom_sim_targets

[riscv-tests.git] / debug / README.md

diff --git a/debug/README.md b/debug/README.md
index 8424b872e4cd7c5c2904814ae0321b1d32314304..56f69db07ec6a1cf6c009a97d1d1314b6b860834 100644 (file)
--- a/debug/README.md
+++ b/debug/README.md
@@ -19,7 +19,7 @@ Targets
 
 `./gdbserver.py --spike32 --cmd $RISCV/bin/spike`
 
-32-bit SiFive Core on Supported FPGA boards
+32-bit SiFive Core on Supported FPGA Boards &  Hardware
 -------------------------------------
 
 `./gdbserver.py --freedom-e300`