Fix test_block for 64-bit targets.

[riscv-tests.git] / debug / gdbserver.py

diff --git a/debug/gdbserver.py b/debug/gdbserver.py
index 0f5c28e50430b3a38257630909dc83c87e1000fd..0310a5befc7424ef6f981a4c022100dd23ca3d89 100755 (executable)
--- a/debug/gdbserver.py
+++ b/debug/gdbserver.py
@@ -43,6 +43,10 @@ class SimpleRegisterTest(DeleteServer):
     def setUp(self):
         self.server = target.server()
         self.gdb = testlib.Gdb()
+        # For now gdb has to be told what the architecture is when it's not
+        # given an ELF file.
+        self.gdb.command("set arch riscv:rv%d" % target.xlen)
+
         self.gdb.command("target extended-remote localhost:%d" % self.server.port)
 
         # 0x13 is nop
@@ -81,9 +85,12 @@ class SimpleMemoryTest(DeleteServer):
     def setUp(self):
         self.server = target.server()
         self.gdb = testlib.Gdb()
+        self.gdb.command("set arch riscv:rv%d" % target.xlen)
         self.gdb.command("target extended-remote localhost:%d" % self.server.port)
 
     def access_test(self, size, data_type):
+        self.assertEqual(self.gdb.p("sizeof(%s)" % data_type),
+                size)
         a = 0x86753095555aaaa & ((1<<(size*8))-1)
         b = 0xdeadbeef12345678 & ((1<<(size*8))-1)
         self.gdb.p("*((%s*)0x%x) = 0x%x" % (data_type, target.ram, a))
@@ -98,7 +105,7 @@ class SimpleMemoryTest(DeleteServer):
         self.access_test(2, 'short')
 
     def test_32(self):
-        self.access_test(4, 'long')
+        self.access_test(4, 'int')
 
     def test_64(self):
         self.access_test(8, 'long long')
@@ -116,7 +123,7 @@ class SimpleMemoryTest(DeleteServer):
 
         self.gdb.command("restore write.ihex 0x%x" % target.ram)
         for offset in range(0, length, 19*4) + [length-4]:
-            value = self.gdb.p("*((long*)0x%x)" % (target.ram + offset))
+            value = self.gdb.p("*((int*)0x%x)" % (target.ram + offset))
             written = ord(data[offset]) | \
                     (ord(data[offset+1]) << 8) | \
                     (ord(data[offset+2]) << 16) | \
@@ -134,6 +141,7 @@ class InstantHaltTest(DeleteServer):
     def setUp(self):
         self.server = target.server()
         self.gdb = testlib.Gdb()
+        self.gdb.command("set arch riscv:rv%d" % target.xlen)
         self.gdb.command("target extended-remote localhost:%d" % self.server.port)
 
     def test_instant_halt(self):
@@ -232,6 +240,9 @@ class DebugTest(DeleteServer):
         self.exit()
 
     def test_hwbp_1(self):
+        if target.instruction_hardware_breakpoint_count < 1:
+            return
+
         self.gdb.hbreak("rot13")
         # The breakpoint should be hit exactly 2 times.
         for i in range(2):
@@ -242,6 +253,9 @@ class DebugTest(DeleteServer):
         self.exit()
 
     def test_hwbp_2(self):
+        if target.instruction_hardware_breakpoint_count < 2:
+            return
+
         self.gdb.hbreak("main")
         self.gdb.hbreak("rot13")
         # We should hit 3 breakpoints.
@@ -444,6 +458,7 @@ class Spike64Target(Target):
     xlen = 64
     ram = 0x80010000
     ram_size = 5 * 1024 * 1024
+    instruction_hardware_breakpoint_count = 0
 
     def server(self):
         return testlib.Spike(parsed.cmd, halted=True)
@@ -454,6 +469,7 @@ class Spike32Target(Target):
     xlen = 32
     ram = 0x80010000
     ram_size = 5 * 1024 * 1024
+    instruction_hardware_breakpoint_count = 0
 
     def server(self):
         return testlib.Spike(parsed.cmd, halted=True, xlen=32)
@@ -463,6 +479,7 @@ class MicroSemiTarget(Target):
     xlen = 32
     ram = 0x80000000
     ram_size = 16 * 1024
+    instruction_hardware_breakpoint_count = 2
 
     def server(self):
         return testlib.Openocd(cmd=parsed.cmd,