Clear triggers during entry.

[riscv-tests.git] / debug / programs / entry.S

diff --git a/debug/programs/entry.S b/debug/programs/entry.S
index 480b404b148f1b3a4316ea04d5f7414d086dd3d5..6dc694f69ea54780ef2a1eb51cb2888c86819924 100755 (executable)
--- a/debug/programs/entry.S
+++ b/debug/programs/entry.S
@@ -3,7 +3,7 @@
 
 #include "encoding.h"
 
-#define STACK_SIZE 128
+#define STACK_SIZE 512
 
 #ifdef __riscv64
 # define LREG ld
@@ -40,6 +40,15 @@ handle_reset:
   # initialize stack pointer
   la sp, stack_top
 
+  # Clear all hardware triggers
+  li    t0, ~0
+1:
+  addi  t0, t0, 1
+  csrw  CSR_TSELECT, t0
+  csrw  CSR_TDATA1, zero
+  csrr  t1, CSR_TSELECT
+  beq   t0, t1, 1b
+
   # perform the rest of initialization in C
   j _init
 
@@ -124,9 +133,9 @@ trap_entry:
   addi sp, sp, 32*REGBYTES
   mret
 
-  .bss
+  // Fill the stack with data so we can see if it was overrun.
   .align 4
 stack_bottom:
-  .skip STACK_SIZE
+  .fill STACK_SIZE/4, 4, 0x22446688
 stack_top:
 #endif