Add abort() for benefit of benchmark code

[riscv-tests.git] / debug / programs / regs.S

diff --git a/debug/programs/regs.S b/debug/programs/regs.S
index e6456e14111a329aabedc4a4467f90d98c8ccf74..200184ddc1bfb519a55158cd5d7e6ac63a745dc8 100644 (file)
--- a/debug/programs/regs.S
+++ b/debug/programs/regs.S
@@ -1,43 +1,57 @@
+#if XLEN == 64
+# define LREG ld
+# define SREG sd
+# define REGBYTES 8
+#else
+# define LREG lw
+# define SREG sw
+# define REGBYTES 4
+#endif
+
+#include "../../env/encoding.h"
+
         .global main
 main:
+        nop
         j       main
 
 write_regs:
-        sd      x1, 0(a0)
-        sd      x2, 8(a0)
-        sd      x3, 16(a0)
-        sd      x4, 24(a0)
-        sd      x5, 32(a0)
-        sd      x6, 40(a0)
-        sd      x7, 48(a0)
-        sd      x8, 56(a0)
-        sd      x9, 64(a0)
-        sd      x11, 72(a0)
-        sd      x12, 80(a0)
-        sd      x13, 88(a0)
-        sd      x14, 96(a0)
-        sd      x15, 104(a0)
-        sd      x16, 112(a0)
-        sd      x17, 120(a0)
-        sd      x18, 128(a0)
-        sd      x19, 136(a0)
-        sd      x20, 144(a0)
-        sd      x21, 152(a0)
-        sd      x22, 160(a0)
-        sd      x23, 168(a0)
-        sd      x24, 176(a0)
-        sd      x25, 184(a0)
-        sd      x26, 192(a0)
-        sd      x27, 200(a0)
-        sd      x28, 208(a0)
-        sd      x29, 216(a0)
-        sd      x30, 224(a0)
-        sd      x31, 232(a0)
+        SREG    x2, 0(x1)
+        SREG    x3, 8(x1)
+        SREG    x4, 16(x1)
+        SREG    x5, 24(x1)
+        SREG    x6, 32(x1)
+        SREG    x7, 40(x1)
+        SREG    x8, 48(x1)
+        SREG    x9, 56(x1)
+        SREG    x10, 64(x1)
+        SREG    x11, 72(x1)
+        SREG    x12, 80(x1)
+        SREG    x13, 88(x1)
+        SREG    x14, 96(x1)
+        SREG    x15, 104(x1)
+        SREG    x16, 112(x1)
+        SREG    x17, 120(x1)
+        SREG    x18, 128(x1)
+        SREG    x19, 136(x1)
+        SREG    x20, 144(x1)
+        SREG    x21, 152(x1)
+        SREG    x22, 160(x1)
+        SREG    x23, 168(x1)
+        SREG    x24, 176(x1)
+        SREG    x25, 184(x1)
+        SREG    x26, 192(x1)
+        SREG    x27, 200(x1)
+        SREG    x28, 208(x1)
+        SREG    x29, 216(x1)
+        SREG    x30, 224(x1)
+        SREG    x31, 232(x1)
 
-        csrr    x1, 1   # fflags
+        csrr    x1, CSR_MSCRATCH
 
 all_done:
         j       all_done
 
+        .balign  16
 data:
         .fill   64, 8, 0