Test step over invalid instruction.

[riscv-tests.git] / debug / programs / step.S

diff --git a/debug/programs/step.S b/debug/programs/step.S
index 49f82d69ded2e894957d064fad468bb0e06f1302..6601548a5614fe158693dbbb3464a6f1b0dd9fc7 100644 (file)
--- a/debug/programs/step.S
+++ b/debug/programs/step.S
@@ -3,15 +3,22 @@
         .global main
 
 main:
-        li      t0, 5                   // 0
-        beq     zero, zero, one         // 0x4
-        nop                             // 0x8
+        la      t0, trap_entry          // 0, 4
+        csrw    mtvec, t0               // 0x8
+
+        li      t0, 5                   // 0xc
+        beq     zero, zero, one         // 0x10
+        nop                             // 0x14
 one:
-        beq     zero, t0, one           // 0xc
-        jal     two                     // 0x10
+        beq     zero, t0, one           // 0x18
+        jal     two                     // 0x1c
 
 three:
-        j       three                   // 0x14
+        .word   0                       // 0x20
+        nop                             // 0x24
 
 two:
-        ret                             // 0x18
+        ret                             // 0x28
+
+trap_entry:
+        j       trap_entry              // 0x2c