debug: Correct the calling for a 32-bit simulation target

[riscv-tests.git] / debug / targets.py

diff --git a/debug/targets.py b/debug/targets.py
index 423ff6955f3c64cc968d6a44a2a203a902bc8463..b8557ce5748e3103a515d823ee68895b63f0f483 100644 (file)
--- a/debug/targets.py
+++ b/debug/targets.py
@@ -107,7 +107,7 @@ class FreedomE300SimTarget(Target):
     openocd_config = "targets/%s/openocd.cfg" % name
 
     def target(self):
-        return testlib.VcsSim(simv=self.sim_cmd, debug=False)
+        return testlib.VcsSim(sim_cmd=self.sim_cmd, debug=False)
 
 class FreedomU500Target(Target):
     name = "freedom-u500"