Add HiFive1 target.

[riscv-tests.git] / debug / targets.py

diff --git a/debug/targets.py b/debug/targets.py
index bcebc0b613ef83797a01fc4dc7d9d77370bf0223..52b623cc59262353b4a84d4582b1a862c1438588 100644 (file)
--- a/debug/targets.py
+++ b/debug/targets.py
@@ -92,6 +92,10 @@ class FreedomE300Target(Target):
     instruction_hardware_breakpoint_count = 2
     openocd_config = "targets/%s/openocd.cfg" % name
 
+class HiFive1Target(FreedomE300Target):
+    name = "HiFive1"
+    openocd_config = "targets/%s/openocd.cfg" % name
+
 class FreedomE300SimTarget(Target):
     name = "freedom-e300-sim"
     xlen = 32
@@ -130,7 +134,8 @@ targets = [
         FreedomE300Target,
         FreedomU500Target,
         FreedomE300SimTarget,
-        FreedomU500SimTarget]
+        FreedomU500SimTarget,
+        HiFive1Target]
 
 def add_target_options(parser):
     group = parser.add_mutually_exclusive_group(required=True)