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Add HiFive1 target.
[riscv-tests.git]
/
debug
/
targets.py
diff --git
a/debug/targets.py
b/debug/targets.py
index ca075ecfcb776682ece1295fec62ade3ae365b02..52b623cc59262353b4a84d4582b1a862c1438588 100644
(file)
--- a/
debug/targets.py
+++ b/
debug/targets.py
@@
-11,6
+11,8
@@
class Target(object):
temporary_files = []
temporary_binary = None
openocd_config = []
temporary_files = []
temporary_binary = None
openocd_config = []
+ use_fpu = False
+ misa = None
def __init__(self, cmd, run, isolate):
self.cmd = cmd
def __init__(self, cmd, run, isolate):
self.cmd = cmd
@@
-38,17
+40,27
@@
class Target(object):
prefix=binary_name + "_")
binary_name = self.temporary_binary.name
Target.temporary_files.append(self.temporary_binary)
prefix=binary_name + "_")
binary_name = self.temporary_binary.name
Target.temporary_files.append(self.temporary_binary)
+ march = "rv%dima" % self.xlen
+ if self.use_fpu:
+ march += "fd"
+ if self.extensionSupported("c"):
+ march += "c"
testlib.compile(sources +
("programs/entry.S", "programs/init.c",
"-I", "../env",
testlib.compile(sources +
("programs/entry.S", "programs/init.c",
"-I", "../env",
- "-march=
RV%dIMAF" % self.xlen
,
+ "-march=
%s" % march
,
"-T", "targets/%s/link.lds" % (self.directory or self.name),
"-nostartfiles",
"-mcmodel=medany",
"-T", "targets/%s/link.lds" % (self.directory or self.name),
"-nostartfiles",
"-mcmodel=medany",
+ "-DXLEN=%d" % self.xlen,
"-o", binary_name),
xlen=self.xlen)
return binary_name
"-o", binary_name),
xlen=self.xlen)
return binary_name
+ def extensionSupported(self, letter):
+ # target.misa is set by testlib.ExamineTarget
+ return self.misa & (1 << (ord(letter.upper()) - ord('A')))
+
class SpikeTarget(Target):
# pylint: disable=abstract-method
directory = "spike"
class SpikeTarget(Target):
# pylint: disable=abstract-method
directory = "spike"
@@
-60,6
+72,7
@@
class SpikeTarget(Target):
class Spike64Target(SpikeTarget):
name = "spike64"
xlen = 64
class Spike64Target(SpikeTarget):
name = "spike64"
xlen = 64
+ use_fpu = True
def server(self):
return testlib.Spike(self.cmd, halted=True)
def server(self):
return testlib.Spike(self.cmd, halted=True)
@@
-79,6
+92,10
@@
class FreedomE300Target(Target):
instruction_hardware_breakpoint_count = 2
openocd_config = "targets/%s/openocd.cfg" % name
instruction_hardware_breakpoint_count = 2
openocd_config = "targets/%s/openocd.cfg" % name
+class HiFive1Target(FreedomE300Target):
+ name = "HiFive1"
+ openocd_config = "targets/%s/openocd.cfg" % name
+
class FreedomE300SimTarget(Target):
name = "freedom-e300-sim"
xlen = 32
class FreedomE300SimTarget(Target):
name = "freedom-e300-sim"
xlen = 32
@@
-117,7
+134,8
@@
targets = [
FreedomE300Target,
FreedomU500Target,
FreedomE300SimTarget,
FreedomE300Target,
FreedomU500Target,
FreedomE300SimTarget,
- FreedomU500SimTarget]
+ FreedomU500SimTarget,
+ HiFive1Target]
def add_target_options(parser):
group = parser.add_mutually_exclusive_group(required=True)
def add_target_options(parser):
group = parser.add_mutually_exclusive_group(required=True)