bump env
[riscv-tests.git] / debug / targets.py
index 423ff6955f3c64cc968d6a44a2a203a902bc8463..63994db87cd252b98839c23ade1597a198b839ae 100644 (file)
+import importlib
 import os.path
+import sys
 import tempfile
 
 import testlib
 
-class Target(object):
-    name = "name"
+class Hart(object):
+    # XLEN of the hart. May be overridden with --32 or --64 command line
+    # options.
     xlen = 0
-    directory = None
-    timeout_sec = 2
-    temporary_files = []
-    temporary_binary = None
-    openocd_config = []
-    use_fpu = False
+
+    # Will be autodetected (by running ExamineTarget) if left unset. Set to
+    # save a little time.
     misa = None
 
-    def __init__(self, server_cmd, sim_cmd, isolate):
-        self.server_cmd = server_cmd
-        self.sim_cmd = sim_cmd
-        self.isolate = isolate
+    # Path to linker script relative to the .py file where the target is
+    # defined. Defaults to <name>.lds.
+    link_script_path = None
+
+    # Implements dmode in tdata1 as described in the spec. Harts that need
+    # this value set to False are not compliant with the spec (but still usable
+    # as long as running code doesn't try to mess with triggers set by an
+    # external debugger).
+    honors_tdata1_hmode = True
+
+    # Address where a r/w/x block of RAM starts, together with its size.
+    ram = None
+    ram_size = None
+
+    # Number of instruction triggers the hart supports.
+    instruction_hardware_breakpoint_count = 0
+
+    # Defaults to target-<index>
+    name = None
+
+    # When reset, the PC must be at one of the values listed here.
+    # This is a list because on some boards the reset vector depends on
+    # jumpers.
+    reset_vectors = []
+
+    def extensionSupported(self, letter):
+        # target.misa is set by testlib.ExamineTarget
+        if self.misa:
+            return self.misa & (1 << (ord(letter.upper()) - ord('A')))
+        else:
+            return False
+
+class Target(object):
+    # pylint: disable=too-many-instance-attributes
+
+    # List of Hart object instances, one for each hart in the target.
+    harts = []
 
-    def target(self):
-        """Start the target, eg. a simulator."""
+    # Name of the target. Defaults to the name of the class.
+    name = None
+
+    # GDB remotetimeout setting.
+    timeout_sec = 2
+
+    # Timeout waiting for the server to start up. This is different than the
+    # GDB timeout, which is how long GDB waits for commands to execute.
+    # The server_timeout is how long this script waits for the server to be
+    # ready for GDB connections.
+    server_timeout_sec = 60
+
+    # Path to OpenOCD configuration file relative to the .py file where the
+    # target is defined. Defaults to <name>.cfg.
+    openocd_config_path = None
+
+    # List of commands that should be executed in gdb after connecting but
+    # before starting the test.
+    gdb_setup = []
+
+    # Supports mtime at 0x2004000
+    supports_clint_mtime = True
+
+    # Implements custom debug registers like spike does. It seems unlikely any
+    # hardware will every do that.
+    implements_custom_test = False
+
+    # Internal variables:
+    directory = None
+    temporary_files = []
+
+    def __init__(self, path, parsed):
+        # Path to module.
+        self.path = path
+        self.directory = os.path.dirname(path)
+        self.server_cmd = parsed.server_cmd
+        self.sim_cmd = parsed.sim_cmd
+        self.temporary_binary = None
+        Target.isolate = parsed.isolate
+        if not self.name:
+            self.name = type(self).__name__
+        # Default OpenOCD config file to <name>.cfg
+        if not self.openocd_config_path:
+            self.openocd_config_path = "%s.cfg" % self.name
+        self.openocd_config_path = os.path.join(self.directory,
+                self.openocd_config_path)
+        for i, hart in enumerate(self.harts):
+            hart.index = i
+            if not hasattr(hart, 'id'):
+                hart.id = i
+            if not hart.name:
+                hart.name = "%s-%d" % (self.name, i)
+            # Default link script to <name>.lds
+            if not hart.link_script_path:
+                hart.link_script_path = "%s.lds" % self.name
+            hart.link_script_path = os.path.join(self.directory,
+                    hart.link_script_path)
+
+    def create(self):
+        """Create the target out of thin air, eg. start a simulator."""
         pass
 
     def server(self):
         """Start the debug server that gdb connects to, eg. OpenOCD."""
-        if self.openocd_config:
-            return testlib.Openocd(server_cmd=self.server_cmd, config=self.openocd_config)
-        else:
-            raise NotImplementedError
+        return testlib.Openocd(server_cmd=self.server_cmd,
+                config=self.openocd_config_path,
+                timeout=self.server_timeout_sec)
 
-    def compile(self, *sources):
+    def compile(self, hart, *sources):
         binary_name = "%s_%s-%d" % (
                 self.name,
                 os.path.basename(os.path.splitext(sources[0])[0]),
-                self.xlen)
-        if self.isolate:
+                hart.xlen)
+        if Target.isolate:
             self.temporary_binary = tempfile.NamedTemporaryFile(
                     prefix=binary_name + "_")
             binary_name = self.temporary_binary.name
             Target.temporary_files.append(self.temporary_binary)
-        march = "rv%dima" % self.xlen
-        if self.use_fpu:
-            march += "fd"
-        if self.extensionSupported("c"):
-            march += "c"
+        march = "rv%dima" % hart.xlen
+        for letter in "fdc":
+            if hart.extensionSupported(letter):
+                march += letter
         testlib.compile(sources +
                 ("programs/entry.S", "programs/init.c",
+                    "-DNHARTS=%d" % len(self.harts),
                     "-I", "../env",
                     "-march=%s" % march,
-                    "-T", "targets/%s/link.lds" % (self.directory or self.name),
+                    "-T", hart.link_script_path,
                     "-nostartfiles",
                     "-mcmodel=medany",
-                    "-DXLEN=%d" % self.xlen,
+                    "-DXLEN=%d" % hart.xlen,
                     "-o", binary_name),
-                xlen=self.xlen)
+                xlen=hart.xlen)
         return binary_name
 
-    def extensionSupported(self, letter):
-        # target.misa is set by testlib.ExamineTarget
-        return self.misa & (1 << (ord(letter.upper()) - ord('A')))
-
-class SpikeTarget(Target):
-    # pylint: disable=abstract-method
-    directory = "spike"
-    ram = 0x10000000
-    ram_size = 0x10000000
-    instruction_hardware_breakpoint_count = 4
-    reset_vector = 0x1000
-    openocd_config = "targets/%s/openocd.cfg" % directory
-
-class Spike64Target(SpikeTarget):
-    name = "spike64"
-    xlen = 64
-    use_fpu = True
-
-    def target(self):
-        return testlib.Spike(self.sim_cmd)
-
-class Spike32Target(SpikeTarget):
-    name = "spike32"
-    xlen = 32
-
-    def target(self):
-        return testlib.Spike(self.sim_cmd, xlen=32)
-
-class FreedomE300Target(Target):
-    name = "freedom-e300"
-    xlen = 32
-    ram = 0x80000000
-    ram_size = 16 * 1024
-    instruction_hardware_breakpoint_count = 2
-    openocd_config = "targets/%s/openocd.cfg" % name
-
-class HiFive1Target(FreedomE300Target):
-    name = "HiFive1"
-    openocd_config = "targets/%s/openocd.cfg" % name
-
-class FreedomE300SimTarget(Target):
-    name = "freedom-e300-sim"
-    xlen = 32
-    timeout_sec = 6000
-    ram = 0x80000000
-    ram_size = 256 * 1024 * 1024
-    instruction_hardware_breakpoint_count = 2
-    openocd_config = "targets/%s/openocd.cfg" % name
-
-    def target(self):
-        return testlib.VcsSim(simv=self.sim_cmd, debug=False)
-
-class FreedomU500Target(Target):
-    name = "freedom-u500"
-    xlen = 64
-    ram = 0x80000000
-    ram_size = 16 * 1024
-    instruction_hardware_breakpoint_count = 2
-    openocd_config = "targets/%s/openocd.cfg" % name
-
-class FreedomU500SimTarget(Target):
-    name = "freedom-u500-sim"
-    xlen = 64
-    timeout_sec = 6000
-    ram = 0x80000000
-    ram_size = 256 * 1024 * 1024
-    instruction_hardware_breakpoint_count = 2
-    openocd_config = "targets/%s/openocd.cfg" % name
-
-    def target(self):
-        return testlib.VcsSim(sim_cmd=self.sim_cmd, debug=False)
-
-targets = [
-        Spike32Target,
-        Spike64Target,
-        FreedomE300Target,
-        FreedomU500Target,
-        FreedomE300SimTarget,
-        FreedomU500SimTarget,
-        HiFive1Target]
-
 def add_target_options(parser):
-    group = parser.add_mutually_exclusive_group(required=True)
-    for t in targets:
-        group.add_argument("--%s" % t.name, action="store_const", const=t,
-                dest="target")
+    parser.add_argument("target", help=".py file that contains definition for "
+            "the target to test with.")
     parser.add_argument("--sim_cmd",
             help="The command to use to start the actual target (e.g. "
-            "simulation)")
+            "simulation)", default="spike")
     parser.add_argument("--server_cmd",
             help="The command to use to start the debug server (e.g. OpenOCD)")
 
     xlen_group = parser.add_mutually_exclusive_group()
-    xlen_group.add_argument("--32", action="store_const", const=32, dest="xlen",
-            help="Force the target to be 32-bit.")
-    xlen_group.add_argument("--64", action="store_const", const=64, dest="xlen",
-            help="Force the target to be 64-bit.")
+    xlen_group.add_argument("--32", action="store_const", const=32,
+            dest="xlen", default=0, help="Force the target to be 32-bit.")
+    xlen_group.add_argument("--64", action="store_const", const=64,
+            dest="xlen", default=0, help="Force the target to be 64-bit.")
 
     parser.add_argument("--isolate", action="store_true",
             help="Try to run in such a way that multiple instances can run at "
             "the same time. This may make it harder to debug a failure if it "
             "does occur.")
+
+def target(parsed):
+    directory = os.path.dirname(parsed.target)
+    filename = os.path.basename(parsed.target)
+    module_name = os.path.splitext(filename)[0]
+
+    sys.path.append(directory)
+    module = importlib.import_module(module_name)
+    found = []
+    for name in dir(module):
+        definition = getattr(module, name)
+        if isinstance(definition, type) and issubclass(definition, Target):
+            found.append(definition)
+    assert len(found) == 1, "%s does not define exactly one subclass of " \
+            "targets.Target" % parsed.target
+
+    t = found[0](parsed.target, parsed)
+    assert t.harts, "%s doesn't have any harts defined!" % t.name
+    if parsed.xlen > 0:
+        for h in t.harts:
+            if h.xlen == 0:
+                h.xlen = parsed.xlen
+            elif h.xlen != parsed.xlen:
+                raise Exception("The target hart specified an XLEN of %d, but "\
+                        "the command line specified an XLEN of %d. They must "\
+                        "match." % (h.xlen, parsed.xlen))
+
+    return t