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Allow multiple reset vectors.
[riscv-tests.git] / debug / targets / RISC-V / spike32.py
diff --git a/debug/targets/RISC-V/spike32.py b/debug/targets/RISC-V/spike32.py
index 665d7e99a56c6ae73e7364a60ef11a33f80b14f5..bcb58927bc0e55205dffa7997edbfafdf94c05f6 100644 (file)
--- a/debug/targets/RISC-V/spike32.py
+++ b/debug/targets/RISC-V/spike32.py
@@ -6,7 +6,7 @@ class spike32_hart(targets.Hart):
     ram = 0x10000000
     ram_size = 0x10000000
     instruction_hardware_breakpoint_count = 4
-    reset_vector = 0x1000
+    reset_vectors = [0x1000]
     link_script_path = "spike32.lds"
 
 class spike32(targets.Target):