Increase dual-core RV64 timeouts.

[riscv-tests.git] / debug / targets / RISC-V / spike64-2-rtos.py

diff --git a/debug/targets/RISC-V/spike64-2-rtos.py b/debug/targets/RISC-V/spike64-2-rtos.py
index d65d2abb24f80fd41b38051e8551a620574f9ce2..7e3fc7e2748b5a8ddeb1d75b63ac14a0e24b8260 100644 (file)
--- a/debug/targets/RISC-V/spike64-2-rtos.py
+++ b/debug/targets/RISC-V/spike64-2-rtos.py
@@ -6,7 +6,7 @@ import spike64  # pylint: disable=import-error
 class spike64_2_rtos(targets.Target):
     harts = [spike64.spike64_hart(), spike64.spike64_hart()]
     openocd_config_path = "spike-rtos.cfg"
-    timeout_sec = 30
+    timeout_sec = 60
 
     def create(self):
         return testlib.Spike(self)