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Make pylint happy.
[riscv-tests.git] / debug / targets / SiFive / Freedom / U500Sim.py
diff --git a/debug/targets/SiFive/Freedom/U500Sim.py b/debug/targets/SiFive/Freedom/U500Sim.py
index 5c500c4842c7a6009a5dca06576d72a19843a133..065ab08ae446b4fb76dba6b9a4968acec34b464c 100644 (file)
--- a/debug/targets/SiFive/Freedom/U500Sim.py
+++ b/debug/targets/SiFive/Freedom/U500Sim.py
@@ -8,7 +8,7 @@ class U500Hart(targets.Hart):
     instruction_hardware_breakpoint_count = 2
     link_script_path = "Freedom.lds"
 
-class U500Sim(Target):
+class U500Sim(targets.Target):
     timeout_sec = 6000
     openocd_config_path = "Freedom.cfg"
     harts = [U500Hart()]