Ensure an error when reading a non-existent CSR.

[riscv-tests.git] / debug / targets / SiFive / HiFive1.cfg

diff --git a/debug/targets/SiFive/HiFive1.cfg b/debug/targets/SiFive/HiFive1.cfg
index 5bde59bb0a26f3174a666e35e5321d239d418421..8f21b4776cb5728e65a8d05cf432b98a5932afbc 100644 (file)
--- a/debug/targets/SiFive/HiFive1.cfg
+++ b/debug/targets/SiFive/HiFive1.cfg
@@ -17,6 +17,10 @@ target create $_TARGETNAME riscv -chain-position $_TARGETNAME
 $_TARGETNAME configure -work-area-phys 0x80000000 -work-area-size 8096 -work-area-backup 1
 #-rtos riscv
 
+# Expose an unimplemented CSR so we can test non-existent register access
+# behavior.
+riscv expose_csrs 2288
+
 flash bank my_first_flash fespi 0x20000000 0 0 0 $_TARGETNAME
 init
 #reset