Added FreedomE300 Simulator target

[riscv-tests.git] / debug / targets / freedom-e300-sim / openocd.cfg

diff --git a/debug/targets/freedom-e300-sim/openocd.cfg b/debug/targets/freedom-e300-sim/openocd.cfg
new file mode 100644 (file)
index 0000000..767d229
--- /dev/null
+++ b/debug/targets/freedom-e300-sim/openocd.cfg
@@ -0,0 +1,19 @@
+adapter_khz     10000
+
+source [find interface/jtag_vpi.cfg]
+
+set _CHIPNAME riscv
+jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x10e31913
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME riscv -chain-position $_TARGETNAME
+
+#reset_config trst_and_srst separate
+# Stupid long so I can see the LEDs
+#adapter_nsrst_delay 2000
+#jtag_ntrst_delay 1000
+#
+init
+#reset
+
+halt