debug: checkpoint of trying to get simulation tests working

[riscv-tests.git] / debug / targets / freedom-e300 / openocd.cfg

diff --git a/debug/targets/freedom-e300/openocd.cfg b/debug/targets/freedom-e300/openocd.cfg
index 0596b15cb5f31cefb2d2857493cfaa3a731150c2..5824b7724a995c180d0f156d3bf92ee00be686a8 100644 (file)
--- a/debug/targets/freedom-e300/openocd.cfg
+++ b/debug/targets/freedom-e300/openocd.cfg
@@ -6,7 +6,7 @@ set _CHIPNAME riscv
 jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x10e31913
 
 set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME riscv -chain-position $_TARGETNAME
+target create $_TARGETNAME riscv -chain-position $_TARGETNAME -rtos riscv
 
 gdb_report_data_abort enable