Add test for memory read from invalid address.

[riscv-tests.git] / debug / targets / freedom-e300 / openocd.cfg

diff --git a/debug/targets/freedom-e300/openocd.cfg b/debug/targets/freedom-e300/openocd.cfg
index d448989243ecc7d893ed4eca399eb2d62b737c76..0596b15cb5f31cefb2d2857493cfaa3a731150c2 100644 (file)
--- a/debug/targets/freedom-e300/openocd.cfg
+++ b/debug/targets/freedom-e300/openocd.cfg
@@ -8,6 +8,8 @@ jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x10e31913
 set _TARGETNAME $_CHIPNAME.cpu
 target create $_TARGETNAME riscv -chain-position $_TARGETNAME
 
 set _TARGETNAME $_CHIPNAME.cpu
 target create $_TARGETNAME riscv -chain-position $_TARGETNAME
 

+gdb_report_data_abort enable
+

 init
 
 halt
 init
 
 halt