Pull port number from VCS output and pass to OpenOCD.

[riscv-tests.git] / debug / targets / freedom-u500-sim / openocd.cfg

diff --git a/debug/targets/freedom-u500-sim/openocd.cfg b/debug/targets/freedom-u500-sim/openocd.cfg
index 767d22963de48571f4efe9bfa35bce9350897f94..0b808858a410a53f876d02fec4a5fc42c52e42e2 100644 (file)
--- a/debug/targets/freedom-u500-sim/openocd.cfg
+++ b/debug/targets/freedom-u500-sim/openocd.cfg
@@ -1,6 +1,7 @@
 adapter_khz     10000
 
 source [find interface/jtag_vpi.cfg]
+jtag_vpi_set_port $::env(JTAG_VPI_PORT)
 
 set _CHIPNAME riscv
 jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x10e31913
@@ -8,12 +9,6 @@ jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x10e31913
 set _TARGETNAME $_CHIPNAME.cpu
 target create $_TARGETNAME riscv -chain-position $_TARGETNAME
 
-#reset_config trst_and_srst separate
-# Stupid long so I can see the LEDs
-#adapter_nsrst_delay 2000
-#jtag_ntrst_delay 1000
-#
 init
-#reset
 
 halt