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Add simple register tests.
[riscv-tests.git]
/
debug
/
targets
/
m2gl_m2s
/
openocd.cfg
diff --git
a/debug/targets/m2gl_m2s/openocd.cfg
b/debug/targets/m2gl_m2s/openocd.cfg
index 0e1a4916800761dc545d256be63773a6bf40e7e1..da20ccc09bf6f4f3edf3eb81a04b87cf288bd4af 100644
(file)
--- a/
debug/targets/m2gl_m2s/openocd.cfg
+++ b/
debug/targets/m2gl_m2s/openocd.cfg
@@
-16,4
+16,4
@@
target create $_TARGETNAME riscv -chain-position $_TARGETNAME
init
#reset
-
#
halt
+halt