Pull port number from VCS output and pass to OpenOCD.

[riscv-tests.git] / debug / testlib.py

diff --git a/debug/testlib.py b/debug/testlib.py
index 29fa1703efdd81f339e726a649e700bac4d77bf1..308bf2157619ceb09f33363a1acbf2ecbe9feb7d 100644 (file)
--- a/debug/testlib.py
+++ b/debug/testlib.py
@@ -102,8 +102,11 @@ class VcsSim(object):
             line = listenfile.readline()
             if not line:
                 time.sleep(1)
-            if "Listening on port 5555" in line:
+            match = re.match(r"^Listening on port (\d+)$", line)
+            if match:
                 done = True
+                self.port = int(match.group(1))
+                print "Using port %d for JTAG VPI" % self.port
 
     def __del__(self):
         try:
@@ -137,11 +140,14 @@ class Openocd(object):
         # line, since they are executed in order.
         cmd[1:1] = ["--command", "gdb_port %d" % self.port]
 
+        env = os.environ.copy()
+        env['JTAG_VPI_PORT'] = str(otherProcess.port)
+
         logfile = open(Openocd.logname, "w")
         logfile.write("+ %s\n" % " ".join(cmd))
         logfile.flush()
         self.process = subprocess.Popen(cmd, stdin=subprocess.PIPE,
-                stdout=logfile, stderr=logfile)
+                stdout=logfile, stderr=logfile, env=env)
 
         # Wait for OpenOCD to have made it through riscv_examine(). When using
         # OpenOCD to communicate with a simulator this may take a long time,