// pass in x0 here.
#define SET_SV_VL( val ) csrrwi x0, 0x4f0, (val-1)
+// set sub-vector length
+#define SET_SV_SUBVL( val ) csrrwi x0, 0x4f4, val
+
#define SV_LD_DATA( reg, from, offs ) \
la x1, from; \
lw reg, offs(x1)
fmv.x.s x2, freg; \
bne x2, x1, fail;
-#define SV_ELWIDTH_TEST(code, load_instruction, testdata, vl, wid1, wid2, wid3, isvec1, isvec2, isvec3, \
- expect1, expect2, expect3 ) \
- \
- load_instruction( x12, testdata , 0); \
- load_instruction( x13, testdata+8 , 0); \
- load_instruction( x14, testdata+16, 0); \
- load_instruction( x15, testdata+24, 0); \
- load_instruction( x16, testdata+32, 0); \
- load_instruction( x17, testdata+40, 0); \
- \
- li x28, 0xa5a5a5a5a5a5a5a5; \
- li x29, 0xa5a5a5a5a5a5a5a5; \
- li x30, 0xa5a5a5a5a5a5a5a5; \
- \
- SET_SV_MVL( vl ); \
- SET_SV_3CSRS( SV_REG_CSR( 1, 15, wid1, 15, isvec1), \
- SV_REG_CSR( 1, 12, wid2, 12, isvec2), \
- SV_REG_CSR( 1, 28, wid3, 28, isvec3)); \
- SET_SV_VL( vl ); \
- \
- code x28, x15, x12; \
- \
- CLR_SV_CSRS(); \
- SET_SV_VL( 1); \
- SET_SV_MVL( 1); \
- \
- TEST_SV_IMM( x28, expect1 ); \
- TEST_SV_IMM( x29, expect2 ); \
- TEST_SV_IMM( x30, expect3 ); \
+// Loads the source registers using load_instruction from testdata with a spacing of elwidth
+#define SV_LOAD_FORMAT(load_instruction, testdata, elwidth) \
+ load_instruction x12, (testdata); \
+ load_instruction x13, (testdata+elwidth); \
+ load_instruction x14, (testdata+elwidth*2); \
+ load_instruction x15, (testdata+elwidth*3); \
+ load_instruction x16, (testdata+elwidth*4); \
+ load_instruction x17, (testdata+elwidth*5); \
+
+// Loads the source registers using load_instruction from testdata with a spacing of elwidth and offset
+#define SV_LOAD_FORMAT_OFFSET(load_instruction, testdata, elwidth, offset) \
+ load_instruction( x12, testdata, offset); \
+ load_instruction( x13, testdata+elwidth, offset); \
+ load_instruction( x14, testdata+elwidth*2, offset); \
+ load_instruction( x15, testdata+elwidth*3, offset); \
+ load_instruction( x16, testdata+elwidth*4, offset); \
+ load_instruction( x17, testdata+elwidth*5, offset); \
+
+// This should be used in all cases where three parameters are formed with an instruction
+// IE addw x28, x15, x12 will be generated
+#define SV_ELWIDTH_TEST(code, load_instruction, testdata, elwidth, offset, \
+ vl, wid1, wid2, wid3, isvec1, isvec2, isvec3, \
+ expect1, expect2, expect3 ) \
+ \
+ SV_ELWIDTH_TEST_INNER(SV_LOAD_FORMAT_OFFSET(load_instruction, testdata, elwidth, offset), \
+ vl, wid1, wid2, wid3, isvec1, isvec2, isvec3, \
+ expect1, expect2, expect3, code x28, x15, x12) \
+
+// This should be used in all cases where two parameters are formed with an instruction
+// IE ld x28 (0)x12 will be generated
+#define SV_ELWIDTH_TEST_LOAD(code, load_instruction, testdata, elwidth, \
+ vl, wid1, wid2, wid3, isvec1, isvec2, isvec3, \
+ expect1, expect2, expect3 ) \
+ \
+ SV_ELWIDTH_TEST_INNER(SV_LOAD_FORMAT(load_instruction, testdata, elwidth), \
+ vl, wid1, wid2, wid3, isvec1, isvec2, isvec3, \
+ expect1, expect2, expect3, code x28, 0(x12)) \
+
+// This should not be accessed directly. It is meant to be called through higher level macros.
+// If used:
+// 1. The 'load_type' parameter should be a SV_LOAD_FORMAT_* macro to
+// generate loading instructions.
+// 2. The 'code' parameter should take on the form of the instruction being tested
+// IE addw x28, x15, x12.
+// Note: The destination register is always 28. The source registers are always 12 and 15
+#define SV_ELWIDTH_TEST_INNER(load_type, vl, wid1, wid2, wid3, \
+ isvec1, isvec2, isvec3, \
+ expect1, expect2, expect3, code... ) \
+ load_type; \
+ \
+ li x28, 0xa5a5a5a5a5a5a5a5; \
+ li x29, 0xa5a5a5a5a5a5a5a5; \
+ li x30, 0xa5a5a5a5a5a5a5a5; \
+ \
+ SET_SV_MVL( vl ); \
+ SET_SV_3CSRS( SV_REG_CSR( 1, 15, wid1, 15, isvec1), \
+ SV_REG_CSR( 1, 12, wid2, 12, isvec2), \
+ SV_REG_CSR( 1, 28, wid3, 28, isvec3)); \
+ SET_SV_VL( vl ); \
+ \
+ code; \
+ \
+ CLR_SV_CSRS(); \
+ SET_SV_VL( 1); \
+ SET_SV_MVL( 1); \
+ \
+ TEST_SV_IMM( x28, expect1 ); \
+ TEST_SV_IMM( x29, expect2 ); \
+ TEST_SV_IMM( x30, expect3 ); \
#define SV_W_DFLT 0
#define SV_W_8BIT 1
#define SV_W_16BIT 2
#define SV_W_32BIT 3
+#define SV_W_DEFAULT_EXPECT 0xa5a5a5a5a5a5a5a5
projects / riscv-tests.git / blobdiff