Merge rv64si and rv32si tests

[riscv-tests.git] / isa / rv32si / illegal.S

diff --git a/isa/rv32si/illegal.S b/isa/rv32si/illegal.S
index 3bec030566f050367d6e704a02b65c9b1ac988ce..ad5c3b1d9c6b19865c6f112d73ce82dda4de2c44 100644 (file)
--- a/isa/rv32si/illegal.S
+++ b/isa/rv32si/illegal.S
@@ -1,43 +1,7 @@
 # See LICENSE for license details.
 
 # See LICENSE for license details.
 

-#*****************************************************************************
-# illegal.S
-#-----------------------------------------------------------------------------
-#
-# Test illegal instruction trap.
-#
-

 #include "riscv_test.h"
 #include "riscv_test.h"

-#include "test_macros.h"
-
-RVTEST_RV32S
-RVTEST_CODE_BEGIN
-
-  la t0, stvec
-  csrw stvec, t0
-
-  li TESTNUM, 2
-  .word 0
-  j fail
-
-  j pass
-
-  TEST_PASSFAIL
-
-stvec:
-  li t1, CAUSE_ILLEGAL_INSTRUCTION
-  csrr t0, scause
-  bne t0, t1, fail
-  csrr t0, sepc
-  addi t0, t0, 8
-  csrw sepc, t0
-  sret
-
-RVTEST_CODE_END
-
-  .data
-RVTEST_DATA_BEGIN
-
-  TEST_DATA
+#undef RVTEST_RV64S
+#define RVTEST_RV64S RVTEST_RV32S

 
 

-RVTEST_DATA_END
+#include "../rv64si/illegal.S"