Merge rv64si and rv32si tests

[riscv-tests.git] / isa / rv32si / ma_addr.S

diff --git a/isa/rv32si/ma_addr.S b/isa/rv32si/ma_addr.S
index 13ac778b059700110af58c7f44437a54379059a2..51465a2eb17932514d719716ba860e229b15733d 100644 (file)
--- a/isa/rv32si/ma_addr.S
+++ b/isa/rv32si/ma_addr.S
@@ -1,89 +1,7 @@
 # See LICENSE for license details.
 
-#*****************************************************************************
-# ma_addr.S
-#-----------------------------------------------------------------------------
-#
-# Test misaligned ld/st trap.
-#
-
 #include "riscv_test.h"
-#include "test_macros.h"
-
-RVTEST_RV32S
-RVTEST_CODE_BEGIN
-
-  la s0, stvec_load
-
-  la t0, stvec_load
-  csrw stvec, t0
-
-  li TESTNUM, 2
-  lw x0, 1(s0)
-  j fail
-
-  li TESTNUM, 3
-  lw x0, 2(s0)
-  j fail
-
-  li TESTNUM, 4
-  lw x0, 3(s0)
-  j fail
-
-  li TESTNUM, 5
-  lh x0, 1(s0)
-  j fail
-
-  li TESTNUM, 6
-  lhu x0, 1(s0)
-  j fail
-
-  la t0, stvec_store
-  csrw stvec, t0
-
-  li TESTNUM, 7
-  sw x0, 1(s0)
-  j fail
-
-  li TESTNUM, 8
-  sw x0, 2(s0)
-  j fail
-
-  li TESTNUM, 9
-  sw x0, 3(s0)
-  j fail
-
-  li TESTNUM, 10
-  sh x0, 1(s0)
-  j fail
-
-  j pass
-
-  TEST_PASSFAIL
-
-stvec_load:
-  li t1, CAUSE_MISALIGNED_LOAD
-  csrr t0, scause
-  bne t0, t1, fail
-  csrr t0, sepc
-  addi t0, t0, 8
-  csrw sepc, t0
-  sret
-
-stvec_store:
-  li t1, CAUSE_MISALIGNED_STORE
-  csrr t0, scause
-  bne t0, t1, fail
-  csrr t0, sepc
-  addi t0, t0, 8
-  csrw sepc, t0
-  sret
-
-RVTEST_CODE_END
-
-  .data
-RVTEST_DATA_BEGIN
-
-  TEST_DATA
+#undef RVTEST_RV64S
+#define RVTEST_RV64S RVTEST_RV32S
 
-RVTEST_DATA_END
+#include "../rv64si/ma_addr.S"