beef up rv32si tests

[riscv-tests.git] / isa / rv32si / privileged.S

diff --git a/isa/rv32si/privileged.S b/isa/rv32si/privileged.S
new file mode 100644 (file)
index 0000000..d827bf5
--- /dev/null
+++ b/isa/rv32si/privileged.S
@@ -0,0 +1,38 @@
+#*****************************************************************************
+# privileged.S
+#-----------------------------------------------------------------------------
+#
+# Test privileged instruction trap.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV32S
+RVTEST_CODE_BEGIN
+
+  la t0, evec
+  csrw evec, t0
+
+  csrci status, 1
+
+  li TESTNUM, 2
+  sret
+  j fail
+
+  TEST_PASSFAIL
+
+evec:
+  li t1, CAUSE_PRIVILEGED_INSTRUCTION
+  csrr t0, cause
+  bne t0, t1, fail
+  j pass
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END