Update to new privileged spec

[riscv-tests.git] / isa / rv32si / sbreak.S

diff --git a/isa/rv32si/sbreak.S b/isa/rv32si/sbreak.S
index 4349b35dae9fba8228038143188d3e68fba7a272..cd920db0240096015d735147ff966c9c7eefc5e0 100644 (file)
--- a/isa/rv32si/sbreak.S
+++ b/isa/rv32si/sbreak.S
@@ -13,8 +13,8 @@
 RVTEST_RV32S
 RVTEST_CODE_BEGIN
 
-  la t0, evec
-  csrw evec, t0
+  la t0, stvec
+  csrw stvec, t0
 
   li TESTNUM, 2
   sbreak
@@ -24,13 +24,13 @@ RVTEST_CODE_BEGIN
 
   TEST_PASSFAIL
 
-evec:
+stvec:
   li t1, CAUSE_BREAKPOINT
-  csrr t0, cause
+  csrr t0, scause
   bne t0, t1, fail
-  csrr t0, epc
+  csrr t0, sepc
   addi t0, t0, 8
-  csrw epc, t0
+  csrw sepc, t0
   sret
 
 RVTEST_CODE_END