Merge rv32ua tests into rv64ua

[riscv-tests.git] / isa / rv32ua / amoand_w.S

diff --git a/isa/rv32ua/amoand_w.S b/isa/rv32ua/amoand_w.S
index 7c989c269f655e6308099b6c82439afea9a373a3..b824483c0d5a9f95643fa669360ec917b825e768 100644 (file)
--- a/isa/rv32ua/amoand_w.S
+++ b/isa/rv32ua/amoand_w.S
@@ -1,65 +1,7 @@
 # See LICENSE for license details.
 
-#*****************************************************************************
-# amoand.w.S
-#-----------------------------------------------------------------------------
-#
-# Test amoand.w instruction.
-#
-
 #include "riscv_test.h"
-#include "test_macros.h"
-
-RVTEST_RV32U
-RVTEST_CODE_BEGIN
-
-  TEST_CASE(2, a4, 0x80000000, \
-    li a0, 0x80000000; \
-    li a1, 0xfffff800; \
-    la a3, amo_operand; \
-    sw a0, 0(a3); \
-    nop; nop; nop; nop; \
-    nop; nop; nop; nop; \
-    nop; nop; nop; nop; \
-    nop; nop; nop; nop; \
-    nop; nop; nop; nop; \
-    nop; nop; nop; nop; \
-    nop; nop; nop; nop; \
-    amoand.w   a4, a1, 0(a3); \
-  )
-
-  TEST_CASE(3, a5, 0x80000000, lw a5, 0(a3))
-
-  # try again after a cache miss
-  TEST_CASE(4, a4, 0x80000000, \
-    li  a1, 0x80000000; \
-    li  a4, 16384; \
-    add a5, a3, a4; \
-    lw  x0, 0(a5); \
-    add a5, a5, a4; \
-    lw  x0, 0(a5); \
-    add a5, a5, a4; \
-    lw  x0, 0(a5); \
-    add a5, a5, a4; \
-    lw  x0, 0(a5); \
-    amoand.w a4, a1, 0(a3); \
-  )
-
-  TEST_CASE(5, a5, 0x80000000, lw a5, 0(a3))
-
-  TEST_PASSFAIL
-
-RVTEST_CODE_END
-
-  .data
-RVTEST_DATA_BEGIN
-
-  TEST_DATA
-
-RVTEST_DATA_END
+#undef RVTEST_RV64U
+#define RVTEST_RV64U RVTEST_RV32U
 
-  .bss
-  .align 3
-amo_operand:
-  .dword 0
-  .skip 65536
+#include "../rv64ua/amoand_w.S"