Enable LR/SC tests, even for uniprocessors

[riscv-tests.git] / isa / rv32ui / Makefrag

diff --git a/isa/rv32ui/Makefrag b/isa/rv32ui/Makefrag
index 95943b75735ad57c0d65395aaf571fa81ce67be3..4bdebb5657438db829cfd0cb6e699b9b57333cda 100644 (file)
--- a/isa/rv32ui/Makefrag
+++ b/isa/rv32ui/Makefrag
@@ -6,6 +6,7 @@ rv32ui_sc_tests = \
        simple \
        add addi \
        amoadd_w amoand_w amomax_w amomaxu_w amomin_w amominu_w amoor_w amoxor_w amoswap_w \
+       lrsc \
        and andi \
        auipc \
        beq bge bgeu blt bltu bne \
@@ -25,12 +26,7 @@ rv32ui_sc_tests = \
        sub \
        xor xori \
 
-rv32ui_mc_tests = \
-       lrsc
-
 rv32ui_p_tests = $(addprefix rv32ui-p-, $(rv32ui_sc_tests))
-rv32ui_pt_tests = $(addprefix rv32ui-pt-, $(rv32ui_sc_tests))
-rv32ui_pm_tests = $(addprefix rv32ui-pm-, $(rv32ui_mc_tests))
 rv32ui_v_tests = $(addprefix rv32ui-v-, $(rv32ui_sc_tests))
 
-spike32_tests += $(rv32ui_p_tests) $(rv32ui_pt_tests) $(rv32ui_pm_tests) $(rv32ui_v_tests)
+spike32_tests += $(rv32ui_p_tests) $(rv32ui_v_tests)