Enable LR/SC tests, even for uniprocessors

[riscv-tests.git] / isa / rv32ui / lrsc.S

diff --git a/isa/rv32ui/lrsc.S b/isa/rv32ui/lrsc.S
index 2332ae096f551e6554cd7c7502148f61509c8d3c..3a3d05a0e22127152a15aee05ecbd85aa30d43b6 100644 (file)
--- a/isa/rv32ui/lrsc.S
+++ b/isa/rv32ui/lrsc.S
@@ -1,3 +1,5 @@
+# See LICENSE for license details.
+
 #*****************************************************************************
 # lrsr.S
 #-----------------------------------------------------------------------------
@@ -11,13 +13,17 @@
 RVTEST_RV32U
 RVTEST_CODE_BEGIN
 
-# wait for all cores to boot
+# get a unique core id
 la a0, coreid
 li a1, 1
 amoadd.w a2, a1, (a0)
-lw a3, 4(x0)
+
+# for now, only run this on core 0
+1:li a3, 1
+bgeu a2, a3, 1b
+
 1: lw a1, (a0)
-blt a1, a3, 1b
+bltu a1, a3, 1b
 
 # make sure that sc without a reservation fails.
 TEST_CASE( 2, a4, 1, \
@@ -26,6 +32,7 @@ TEST_CASE( 2, a4, 1, \
 )
 
 # make sure that sc with the wrong reservation fails.
+# TODO is this actually mandatory behavior?
 TEST_CASE( 3, a4, 1, \
   la a0, foo; \
   add a1, a0, 1024; \