Enable LR/SC tests, even for uniprocessors

[riscv-tests.git] / isa / rv32ui / lrsc.S

diff --git a/isa/rv32ui/lrsc.S b/isa/rv32ui/lrsc.S
index 2aee81802a287f597ee2e38865e81f21f7f5b178..3a3d05a0e22127152a15aee05ecbd85aa30d43b6 100644 (file)
--- a/isa/rv32ui/lrsc.S
+++ b/isa/rv32ui/lrsc.S
@@ -32,6 +32,7 @@ TEST_CASE( 2, a4, 1, \
 )
 
 # make sure that sc with the wrong reservation fails.
+# TODO is this actually mandatory behavior?
 TEST_CASE( 3, a4, 1, \
   la a0, foo; \
   add a1, a0, 1024; \