Fixed srl, srli

[riscv-tests.git] / isa / rv32ui / srl.S

diff --git a/isa/rv32ui/srl.S b/isa/rv32ui/srl.S
index 8f8719d771ccb411ec0c278f51af821292bd4100..d1de5cec223240bf0b358c3aa982556055d1200e 100644 (file)
--- a/isa/rv32ui/srl.S
+++ b/isa/rv32ui/srl.S
@@ -35,10 +35,10 @@ RVTEST_CODE_BEGIN
 
   # Verify that shifts only use bottom five bits
 
-  TEST_RR_OP( 17, srl, 0x21212121, 0x21212121, 0xffffffc0 );
-  TEST_RR_OP( 18, srl, 0x10909090, 0x21212121, 0xffffffc1 );
-  TEST_RR_OP( 19, srl, 0x00424242, 0x21212121, 0xffffffc7 );
-  TEST_RR_OP( 20, srl, 0x00008484, 0x21212121, 0xffffffce );
+  TEST_RR_OP( 17, srl, 0x21212121, 0x21212121, 0xffffffe0 );
+  TEST_RR_OP( 18, srl, 0x10909090, 0x21212121, 0xffffffe1 );
+  TEST_RR_OP( 19, srl, 0x00424242, 0x21212121, 0xffffffe7 );
+  TEST_RR_OP( 20, srl, 0x00008484, 0x21212121, 0xffffffee );
   TEST_RR_OP( 21, srl, 0x00000000, 0x21212121, 0xffffffff );
 
   #-------------------------------------------------------------