Revert "breakpoint.S: Don't assume trigger is hardwired to breakpoint (#158) (#159)"

[riscv-tests.git] / isa / rv64mi / breakpoint.S

diff --git a/isa/rv64mi/breakpoint.S b/isa/rv64mi/breakpoint.S
index 5e4dfbb9987ef71dd376aa4f704ee71910ee130f..647430b8daa5865b836cd8caf255b8f63b58a004 100644 (file)
--- a/isa/rv64mi/breakpoint.S
+++ b/isa/rv64mi/breakpoint.S
@@ -16,87 +16,119 @@ RVTEST_CODE_BEGIN
   # Set up breakpoint to trap on M-mode fetches.
   li TESTNUM, 2
 
-  # Skip tdrselect is hard-wired.
-  li t0, 1<<(_RISCV_SZLONG-1)
-  csrw tdrselect, t0
-  csrr t1, tdrselect
-  bne t0, t1, pass
+  # Skip tselect if hard-wired.
+  csrw tselect, x0
+  csrr a1, tselect
+  bne x0, a1, pass
 
   # Make sure there's a breakpoint there.
-  csrr t0, tdrdata1
-  srli t0, t0, _RISCV_SZLONG-4
-  li t1, 1
-  bne t0, t1, pass
-
-  la t2, 1f
-  csrw tdrdata2, t2
-  li t0, BPCONTROL_M | BPCONTROL_X
-  csrw tdrdata1, t0
+  csrr a0, tdata1
+  srli a0, a0, __riscv_xlen - 4
+  li a1, 2
+  bne a0, a1, pass
+
+  la a2, 1f
+  csrw tdata2, a2
+  li a0, MCONTROL_M | MCONTROL_EXECUTE
+  csrw tdata1, a0
   # Skip if breakpoint type is unsupported.
-  csrr t1, tdrdata1
-  andi t1, t1, 0x7ff
-  bne t0, t1, 2f
+  csrr a1, tdata1
+  andi a1, a1, 0x7ff
+  bne a0, a1, 2f
+  .align 2
 1:
   # Trap handler should skip this instruction.
-  j fail
+  beqz x0, fail
 
   # Make sure reads don't trap.
   li TESTNUM, 3
-  lw t0, (t2)
+  lw a0, (a2)
 
 2:
   # Set up breakpoint to trap on M-mode reads.
   li TESTNUM, 4
-  li t0, BPCONTROL_M | BPCONTROL_R
-  csrw tdrdata1, t0
+  li a0, MCONTROL_M | MCONTROL_LOAD
+  csrw tdata1, a0
   # Skip if breakpoint type is unsupported.
-  csrr t1, tdrdata1
-  andi t1, t1, 0x7ff
-  bne t0, t1, 2f
-  la t2, write_data
-  csrw tdrdata2, t2
+  csrr a1, tdata1
+  andi a1, a1, 0x7ff
+  bne a0, a1, 2f
+  la a2, data1
+  csrw tdata2, a2
 
   # Trap handler should skip this instruction.
-  lw t2, (t2)
-  beqz t2, fail
+  lw a2, (a2)
+  beqz a2, fail
 
   # Make sure writes don't trap.
   li TESTNUM, 5
-  sw x0, (t2)
+  sw x0, (a2)
 
 2:
   # Set up breakpoint to trap on M-mode stores.
   li TESTNUM, 6
-  li t0, BPCONTROL_M | BPCONTROL_W
-  csrw tdrdata1, t0
+  li a0, MCONTROL_M | MCONTROL_STORE
+  csrw tdata1, a0
   # Skip if breakpoint type is unsupported.
-  csrr t1, tdrdata1
-  andi t1, t1, 0x7ff
-  bne t0, t1, 2f
+  csrr a1, tdata1
+  andi a1, a1, 0x7ff
+  bne a0, a1, 2f
 
   # Trap handler should skip this instruction.
-  sw t2, (t2)
+  sw a2, (a2)
 
   # Make sure store didn't succeed.
   li TESTNUM, 7
-  lw t2, (t2)
-  bnez t2, fail
+  lw a2, (a2)
+  bnez a2, fail
+
+  # Try to set up a second breakpoint.
+  li a0, 1
+  csrw tselect, a0
+  csrr a1, tselect
+  bne a0, a1, pass
+
+  # Make sure there's a breakpoint there.
+  csrr a0, tdata1
+  srli a0, a0, __riscv_xlen - 4
+  li a1, 2
+  bne a0, a1, pass
+
+  li a0, MCONTROL_M | MCONTROL_LOAD
+  csrw tdata1, a0
+  la a3, data2
+  csrw tdata2, a3
+
+  # Make sure the second breakpoint triggers.
+  li TESTNUM, 8
+  lw a3, (a3)
+  beqz a3, fail
+
+  # Make sure the first breakpoint still triggers.
+  li TESTNUM, 10
+  la a2, data1
+  sw a2, (a2)
+  li TESTNUM, 11
+  lw a2, (a2)
+  bnez a2, fail
 
 2:
   TEST_PASSFAIL
 
+  .align 2
+  .global mtvec_handler
 mtvec_handler:
   # Only even-numbered tests should trap.
-  andi a0, TESTNUM, 1
-  bnez a0, fail
+  andi t0, TESTNUM, 1
+  bnez t0, fail
 
-  li a0, CAUSE_BREAKPOINT
-  csrr a1, mcause
-  bne a0, a1, fail
+  li t0, CAUSE_BREAKPOINT
+  csrr t1, mcause
+  bne t0, t1, fail
 
-  csrr a0, mepc
-  addi a0, a0, 4
-  csrw mepc, a0
+  csrr t0, mepc
+  addi t0, t0, 4
+  csrw mepc, t0
   mret
 
 RVTEST_CODE_END
@@ -106,6 +138,7 @@ RVTEST_DATA_BEGIN
 
   TEST_DATA
 
-write_data: .word 0
+data1: .word 0
+data2: .word 0
 
 RVTEST_DATA_END