Revert "breakpoint.S: Don't assume trigger is hardwired to breakpoint (#158) (#159)"

[riscv-tests.git] / isa / rv64mi / breakpoint.S

diff --git a/isa/rv64mi/breakpoint.S b/isa/rv64mi/breakpoint.S
index b318c30399e0ce815ac7471a8c33d031a272ed27..647430b8daa5865b836cd8caf255b8f63b58a004 100644 (file)
--- a/isa/rv64mi/breakpoint.S
+++ b/isa/rv64mi/breakpoint.S
@@ -23,7 +23,7 @@ RVTEST_CODE_BEGIN
 
   # Make sure there's a breakpoint there.
   csrr a0, tdata1
-  srli a0, a0, _RISCV_SZLONG-4
+  srli a0, a0, __riscv_xlen - 4
   li a1, 2
   bne a0, a1, pass
 
@@ -90,7 +90,7 @@ RVTEST_CODE_BEGIN
 
   # Make sure there's a breakpoint there.
   csrr a0, tdata1
-  srli a0, a0, _RISCV_SZLONG-4
+  srli a0, a0, __riscv_xlen - 4
   li a1, 2
   bne a0, a1, pass
 
@@ -115,6 +115,8 @@ RVTEST_CODE_BEGIN
 2:
   TEST_PASSFAIL
 
+  .align 2
+  .global mtvec_handler
 mtvec_handler:
   # Only even-numbered tests should trap.
   andi t0, TESTNUM, 1