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Clear triggers during entry.
[riscv-tests.git] / isa / rv64mi / illegal.S
diff --git a/isa/rv64mi/illegal.S b/isa/rv64mi/illegal.S
index ecb308889dac4c0269c39cabc98610ca3007f56e..30c22b264fcadf55d66d5673e7d283fae18d9bda 100644 (file)
--- a/isa/rv64mi/illegal.S
+++ b/isa/rv64mi/illegal.S
@@ -28,7 +28,7 @@ mtvec_handler:
   csrr t0, mepc
   addi t0, t0, 8
   csrw mepc, t0
-  sret
+  mret
 
 RVTEST_CODE_END