RVTEST_CODE_BEGIN
# enable interrupts
- csrs mstatus, MSTATUS_IE
+ csrs mstatus, MSTATUS_MIE
+ csrs mie, MIP_MSIP
# get a unique core id
la a0, coreid
1:li a3, 1
bgeu a2, a3, 1b
- # wait for all cores to boot
- 1: lw a1, (a0)
- bltu a1, a3, 1b
-
- # IPI dominoes
- csrr a0, hartid
- 1: bnez a0, 1b
- add a0, a0, 1
- rem a0, a0, a3
- csrw send_ipi, a0
+ # send a self-IPI
+ csrwi mipi, 1
1: j 1b
mtvec_handler:
- csrr a0, hartid
- bnez a0, 2f
+ bnez a2, fail
RVTEST_PASS
TEST_PASSFAIL
- 2: add a0, a0, 1
- rem a0, a0, a3
- csrw send_ipi, a0
- 1: j 1b
-
RVTEST_CODE_END
.data