Remove instruction width assumptions to support RVC

[riscv-tests.git] / isa / rv64mi / ma_addr.S

diff --git a/isa/rv64mi/ma_addr.S b/isa/rv64mi/ma_addr.S
index ed177f5a11682ff5c70acb958e427c12b7bd2c59..c84242a99c4d9d817305f50bde104375e59d154e 100644 (file)
--- a/isa/rv64mi/ma_addr.S
+++ b/isa/rv64mi/ma_addr.S
@@ -14,6 +14,7 @@ RVTEST_RV64M
 RVTEST_CODE_BEGIN
 
   .align 3
+  .option norvc
   auipc s0, 0
 
   # indicate it's a load test