Clear triggers during entry.

[riscv-tests.git] / isa / rv64mi / ma_addr.S

diff --git a/isa/rv64mi/ma_addr.S b/isa/rv64mi/ma_addr.S
index aa5dd8503d3d79f28312822752101187495e4e2d..6e7be9480b47e8d530e6615d7ba06cf8ac55b802 100644 (file)
--- a/isa/rv64mi/ma_addr.S
+++ b/isa/rv64mi/ma_addr.S
@@ -13,8 +13,9 @@
 RVTEST_RV64M
 RVTEST_CODE_BEGIN
 
-  .align 3
-  auipc s0, 0
+  .option norvc
+
+  la s0, data
 
   # indicate it's a load test
   li s1, CAUSE_MISALIGNED_LOAD
@@ -72,13 +73,16 @@ mtvec_handler:
   csrr t0, mepc
   addi t0, t0, 8
   csrw mepc, t0
-  sret
+  mret
 
 RVTEST_CODE_END
 
   .data
 RVTEST_DATA_BEGIN
 
+data:
+  .dword 0
+
   TEST_DATA
 
 RVTEST_DATA_END