Check mbadaddr in ma_addr test

[riscv-tests.git] / isa / rv64mi / ma_addr.S

diff --git a/isa/rv64mi/ma_addr.S b/isa/rv64mi/ma_addr.S
index 6e7be9480b47e8d530e6615d7ba06cf8ac55b802..ba96606335e9acd6322cbaf2eb8502d508489d09 100644 (file)
--- a/isa/rv64mi/ma_addr.S
+++ b/isa/rv64mi/ma_addr.S
@@ -22,6 +22,7 @@ RVTEST_CODE_BEGIN
 
 #define MISALIGNED_LDST_TEST(testnum, insn, base, offset) \
   li TESTNUM, testnum; \
+  addi t1, base, offset; \
   insn x0, offset(base); \
   j fail \
 
@@ -31,7 +32,7 @@ RVTEST_CODE_BEGIN
   MISALIGNED_LDST_TEST(5,  lw,  s0, 2)
   MISALIGNED_LDST_TEST(6,  lw,  s0, 3)
 
-#ifdef __riscv64
+#if __riscv_xlen == 64
   MISALIGNED_LDST_TEST(7,  lwu, s0, 1)
   MISALIGNED_LDST_TEST(8,  lwu, s0, 2)
   MISALIGNED_LDST_TEST(9,  lwu, s0, 3)
@@ -53,7 +54,7 @@ RVTEST_CODE_BEGIN
   MISALIGNED_LDST_TEST(24,  sw,  s0, 2)
   MISALIGNED_LDST_TEST(25,  sw,  s0, 3)
 
-#ifdef __riscv64
+#if __riscv_xlen == 64
   MISALIGNED_LDST_TEST(26, sd, s0, 1)
   MISALIGNED_LDST_TEST(27, sd, s0, 2)
   MISALIGNED_LDST_TEST(28, sd, s0, 3)
@@ -70,6 +71,9 @@ mtvec_handler:
   csrr t0, mcause
   bne t0, s1, fail
 
+  csrr t0, mbadaddr
+  bne t0, t1, fail
+
   csrr t0, mepc
   addi t0, t0, 8
   csrw mepc, t0