Pass newly updated -march, -mabi options to gcc

[riscv-tests.git] / isa / rv64mi / ma_addr.S

diff --git a/isa/rv64mi/ma_addr.S b/isa/rv64mi/ma_addr.S
index aa5dd8503d3d79f28312822752101187495e4e2d..be3572fec37de1ca9be65f917c71a26f560b60e0 100644 (file)
--- a/isa/rv64mi/ma_addr.S
+++ b/isa/rv64mi/ma_addr.S
@@ -13,8 +13,9 @@
 RVTEST_RV64M
 RVTEST_CODE_BEGIN
 
-  .align 3
-  auipc s0, 0
+  .option norvc
+
+  la s0, data
 
   # indicate it's a load test
   li s1, CAUSE_MISALIGNED_LOAD
@@ -30,7 +31,7 @@ RVTEST_CODE_BEGIN
   MISALIGNED_LDST_TEST(5,  lw,  s0, 2)
   MISALIGNED_LDST_TEST(6,  lw,  s0, 3)
 
-#ifdef __riscv64
+#if __riscv_xlen == 64
   MISALIGNED_LDST_TEST(7,  lwu, s0, 1)
   MISALIGNED_LDST_TEST(8,  lwu, s0, 2)
   MISALIGNED_LDST_TEST(9,  lwu, s0, 3)
@@ -52,7 +53,7 @@ RVTEST_CODE_BEGIN
   MISALIGNED_LDST_TEST(24,  sw,  s0, 2)
   MISALIGNED_LDST_TEST(25,  sw,  s0, 3)
 
-#ifdef __riscv64
+#if __riscv_xlen == 64
   MISALIGNED_LDST_TEST(26, sd, s0, 1)
   MISALIGNED_LDST_TEST(27, sd, s0, 2)
   MISALIGNED_LDST_TEST(28, sd, s0, 3)
@@ -72,13 +73,16 @@ mtvec_handler:
   csrr t0, mepc
   addi t0, t0, 8
   csrw mepc, t0
-  sret
+  mret
 
 RVTEST_CODE_END
 
   .data
 RVTEST_DATA_BEGIN
 
+data:
+  .dword 0
+
   TEST_DATA
 
 RVTEST_DATA_END