ERET -> xRET; new memory map

[riscv-tests.git] / isa / rv64mi / ma_addr.S

diff --git a/isa/rv64mi/ma_addr.S b/isa/rv64mi/ma_addr.S
index aa5dd8503d3d79f28312822752101187495e4e2d..ed177f5a11682ff5c70acb958e427c12b7bd2c59 100644 (file)
--- a/isa/rv64mi/ma_addr.S
+++ b/isa/rv64mi/ma_addr.S
@@ -72,7 +72,7 @@ mtvec_handler:
   csrr t0, mepc
   addi t0, t0, 8
   csrw mepc, t0
-  sret
+  mret
 
 RVTEST_CODE_END