Clear triggers during entry.

[riscv-tests.git] / isa / rv64mi / mcsr.S

diff --git a/isa/rv64mi/mcsr.S b/isa/rv64mi/mcsr.S
index 2eeb14cdb6247f977ee2d79a8606fbbb09e2b6ac..b66611c86594d2108e7e7f94e674ba6a5ecfd758 100644 (file)
--- a/isa/rv64mi/mcsr.S
+++ b/isa/rv64mi/mcsr.S
@@ -17,20 +17,29 @@ RVTEST_CODE_BEGIN
 #ifdef __riscv64
   TEST_CASE(2, a0, 0x2, csrr a0, misa; srl a0, a0, 62)
 #else
-  TEST_CASE(2, a0, 0x0, csrr a0, misa; srl a0, a0, 30)
+  TEST_CASE(2, a0, 0x1, csrr a0, misa; srl a0, a0, 30)
 #endif
 
   # Check that mhartid reports 0
   TEST_CASE(3, a0, 0x0, csrr a0, mhartid)
 
-  # Check that reading mimpid, marchid, and mvendorid doesn't cause exceptions
+  # Check that reading the following CSRs doesn't cause an exception
   csrr a0, mimpid
   csrr a0, marchid
   csrr a0, mvendorid
 
-  # Check that mtvec reports DEFAULT_MTVEC
-  TEST_CASE(5, a0, DEFAULT_MTVEC, csrr a0, mtvec)
+  # Check that writing hte following CSRs doesn't cause an exception
+  li t0, 0
+  csrs mtvec, t0
+  csrs mepc, t0
 
   TEST_PASSFAIL
 
 RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END