Clear triggers during entry.

[riscv-tests.git] / isa / rv64mi / mcsr.S

diff --git a/isa/rv64mi/mcsr.S b/isa/rv64mi/mcsr.S
index f7048275dcc215469ea31367bcfecaa76f2cac18..b66611c86594d2108e7e7f94e674ba6a5ecfd758 100644 (file)
--- a/isa/rv64mi/mcsr.S
+++ b/isa/rv64mi/mcsr.S
@@ -36,3 +36,10 @@ RVTEST_CODE_BEGIN
   TEST_PASSFAIL
 
 RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END