Pass newly updated -march, -mabi options to gcc

[riscv-tests.git] / isa / rv64mi / mcsr.S

diff --git a/isa/rv64mi/mcsr.S b/isa/rv64mi/mcsr.S
index 4bb04454c0808ec3c0c0e91ea2877a1520c73e93..e0256e7ef3cadc8d5f9cc1928679d185c3349af0 100644 (file)
--- a/isa/rv64mi/mcsr.S
+++ b/isa/rv64mi/mcsr.S
@@ -14,7 +14,7 @@ RVTEST_RV64M
 RVTEST_CODE_BEGIN
 
   # Check that mcpuid reports the correct XLEN
-#ifdef __riscv64
+#if __riscv_xlen == 64
   TEST_CASE(2, a0, 0x2, csrr a0, misa; srl a0, a0, 62)
 #else
   TEST_CASE(2, a0, 0x1, csrr a0, misa; srl a0, a0, 30)
@@ -23,14 +23,23 @@ RVTEST_CODE_BEGIN
   # Check that mhartid reports 0
   TEST_CASE(3, a0, 0x0, csrr a0, mhartid)
 
-  # Check that reading mimpid, marchid, and mvendorid doesn't cause exceptions
+  # Check that reading the following CSRs doesn't cause an exception
   csrr a0, mimpid
   csrr a0, marchid
   csrr a0, mvendorid
 
-  # Check that mtvec reports DEFAULT_MTVEC
-  TEST_CASE(5, a0, DEFAULT_MTVEC, csrr a0, mtvec)
+  # Check that writing hte following CSRs doesn't cause an exception
+  li t0, 0
+  csrs mtvec, t0
+  csrs mepc, t0
 
   TEST_PASSFAIL
 
 RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END