ERET -> xRET; new memory map

[riscv-tests.git] / isa / rv64mi / mcsr.S

diff --git a/isa/rv64mi/mcsr.S b/isa/rv64mi/mcsr.S
index c1e2cd3402946630dd3dcbe5c2d6f196e6678a72..f7048275dcc215469ea31367bcfecaa76f2cac18 100644 (file)
--- a/isa/rv64mi/mcsr.S
+++ b/isa/rv64mi/mcsr.S
@@ -13,17 +13,25 @@
 RVTEST_RV64M
 RVTEST_CODE_BEGIN
 
-  # Check that mcpuid reports RV64
-  TEST_CASE(2, a0, 0x2, csrr a0, mcpuid; srl a0, a0, 62)
+  # Check that mcpuid reports the correct XLEN
+#ifdef __riscv64
+  TEST_CASE(2, a0, 0x2, csrr a0, misa; srl a0, a0, 62)
+#else
+  TEST_CASE(2, a0, 0x1, csrr a0, misa; srl a0, a0, 30)
+#endif
 
   # Check that mhartid reports 0
   TEST_CASE(3, a0, 0x0, csrr a0, mhartid)
 
-  # Check that mimpid reports UC Berkeley
-  TEST_CASE(4, a0, 0x1, csrr a0, mimpid; sll a0, a0, 48; srl a0, a0, 48)
+  # Check that reading the following CSRs doesn't cause an exception
+  csrr a0, mimpid
+  csrr a0, marchid
+  csrr a0, mvendorid
 
-  # Check that mtvec reports DEFAULT_MTVEC
-  TEST_CASE(5, a0, DEFAULT_MTVEC, csrr a0, mtvec)
+  # Check that writing hte following CSRs doesn't cause an exception
+  li t0, 0
+  csrs mtvec, t0
+  csrs mepc, t0
 
   TEST_PASSFAIL