Don't use stats register; refer to uarch counters by number

[riscv-tests.git] / isa / rv64mi / timer.S

diff --git a/isa/rv64mi/timer.S b/isa/rv64mi/timer.S
index b7cc633613f8cd57e70165ecd6a69fd00f18c6c7..4697793baf9b61f00506021d1d0b6bfa8eb679ea 100644 (file)
--- a/isa/rv64mi/timer.S
+++ b/isa/rv64mi/timer.S
@@ -24,7 +24,7 @@ RVTEST_CODE_BEGIN
   csrw mtimecmp, a0
   li a0, MIP_MTIP
   csrs mie, a0
-  csrs mstatus, MSTATUS_IE
+  csrs mstatus, MSTATUS_MIE
 
   # advance an LFSR until the timer has fired enough times
   li s0, 1023
@@ -64,7 +64,7 @@ mtvec_handler:
   bgez t0, fail
 
   sll t0, t0, 1
-  addi t0, t0, -2*IRQ_TIMER
+  addi t0, t0, -2*IRQ_M_TIMER
   bnez t0, fail
 
   csrr t0, mtime