Remove instruction width assumptions to support RVC

[riscv-tests.git] / isa / rv64si / csr.S

diff --git a/isa/rv64si/csr.S b/isa/rv64si/csr.S
index 35fc99a52feed5f0cc7a5613983ab4075afbb65d..3858daad556f3632d5d5c2f8035f3a5c62dbf79b 100644 (file)
--- a/isa/rv64si/csr.S
+++ b/isa/rv64si/csr.S
@@ -61,6 +61,7 @@ RVTEST_CODE_BEGIN
   # We should only fall through to this if scall failed.
   TEST_PASSFAIL
 
+  .align 2
 stvec_handler:
   # Trapping on tests 10 and 11 is good news.
   # Note that since the test didn't complete, TESTNUM is smaller by 1.