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Merge [shm]call into ecall, [shm]ret into eret
[riscv-tests.git]
/
isa
/
rv64si
/
dirty.S
diff --git
a/isa/rv64si/dirty.S
b/isa/rv64si/dirty.S
index 87a619ab999bd3a4fa22d232bbcb4db743bded09..78e333b62995714cccf891d4c5013a3fcf301840 100644
(file)
--- a/
isa/rv64si/dirty.S
+++ b/
isa/rv64si/dirty.S
@@
-23,7
+23,7
@@
RVTEST_CODE_BEGIN
csrs mstatus, a1
la a1, 1f
csrw mepc, a1
csrs mstatus, a1
la a1, 1f
csrw mepc, a1
-
m
ret
+
e
ret
1:
# Try a faulting store to make sure dirty bit is not set
1:
# Try a faulting store to make sure dirty bit is not set